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ADE7880
Data Sheet
to 750 ms, the settling time of the harmonic calculations. Other
possible values are 500 ms (HSTIME = 00), 1 sec (10) and 1250
ms (11).
?
?
Initialize the gain registers used in the harmonic
calculations. Leave the offset registers to 0.
Read the registers in which the harmonic in formation is
The secon d approach, enabled when Bit 0 (HRCFG) of
HCONFIG register is set to 1, sets Bit 19 (HREADY) in
STATUS0 register to 1 every time the harmonic calculatio ns are
updated at the update frequency determined by HRATE bits
without waiting for the harmonic calculations to settle. This
allows an external microcontroller to access the harmonic
calculations immediately after they have been started. If the
corresponding mask bit in the MASK0 interrupt mask register
is enabled, the IRQ pin also goes active low. The status bit is
cleared and the pin IRQ is set to high again by writing to the
STATUS0 register with the corresponding bit set to 1.
stored using the burst or regular reading mode at high to
low transitions of CF2/HREADY pin.
WA VEFORM SAMPLING MODE
The waveform samples of the current an d voltage waveform,
the active, reactive, and apparent power outputs are stored
every 125 μs (8 kHz rate) into 24-bit signed registers that can be
accessed through various serial ports of the ADE7880 . Table 22
provides a list of registers and their descriptions.
Table 22. Waveform Registers List
Register Description
Additionally, the ADE7880 provides a periodical output signal
called HREADY at the CF2/HREADY pin synchronous to the
moment the harmonic calculations are updated in the harmoni c
registers. This functionality is chosen if Bit 2 (CF2DIS) is set to
1 in the CONFIG register. If CF2DIS is set to 0 (default value),
the CF2 energy to frequency converter output is provided at
CF2/HREADY pin. The default state of this signal is high. Ever y
time the harmonic registers are updated based on HRATE bits
in HCONFIG register, the signal HREADY goes low for
approximately 10 μsec and then goes back high. If Bit 0
(HRCFG) in the HCONFIG register is 0, that is the HRE ADY
bit in the STATUS1 register is set to 1 every HRATE period
right after the harmonic calculations have started, the signal
IAWV
VAWV
IBWV
VBWV
ICWV
VCWV
INWV
AVA
BVA
CVA
AWATT
BWATT
CWATT
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Phase C current
Phase C voltage
Neutral current
Phase A apparent power
Phase B apparent power
Phase C apparent power
Phase A active power
Phase B active power
Phase C active power
HREADY toggles high, low and back synchronously. If the
HRCFG bit is 1, that is, Bit HREADY in the STATUS1 regist er
is set to 1 after the HSTIME period, the HREADY signal toggle s
high, low and back synchronously. The HREADY signal allows
fast access to the harmonic registers without having to use
HREADY interrupt in MASK1 register.
In order to facilitate the fast reading of th e registers in which
the harmonic calculations are stored, a special burst registers
reading has been implemented in the serial interfaces. See the
I 2 C Read Operation of Harmonic Calculations Registers and th e
SPI Read Operation sections for details.
Recommended Approach to Managi ng Harmonic
Calculations
The recommen ded approach to managing the ADE7880
harmonic calculations is the following:
? Set up Bit 2 (CF2DIS) in the CONF IG register. Set the
CF2DIS bit to 1 to use the CF2/HREADY pin to signal
when the harmonic calculations have settled and are
updated. The high to low transition of HREADY signal
indicates when to read the harmonic registers. Use the
burst reading mode to read the harmonic registers as it i s
the most efficient way to read them.
? Choose the harmonics to be monitore d by setting HX, HY
and HZ appropriately.
Bit 17 (DREADY) i n the STATUS0 register can be used to
signal when the registers listed in Table 22 can be read usin g
I 2 C or SPI serial ports. An interrupt attached to the flag can be
enabled by setting Bit 17 (DREADY) in the MASK0 register. (see
the Digital Signal Processor section for more details on
Bit DREADY).
The ADE7880 co ntains a high speed data capture (HSDC) port
that is specially designed to provide fast access to the waveform
sample registers. Read the HSDC Interface section for more
details.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
All registers listed in Table 22 are transmitted signed extended
from 24 bits to 32 bits (see Figure 44).
ENERGY-TO-FREQUENCY CONV ERSION
The ADE7880 provides three frequency output pins : CF1, CF2,
and CF3. The CF2 pin is multiplexed with the HREADY pin of
the harmonic calculations block. When HREADY is enabled,
the CF2 functionality is disabled at the pin. The CF3 pin is
multiplexed with the HSCLK pin of the HSDC interface. Whe n
HSDC is enabled, the CF3 functionality is disabled at the pin.
CF1 pin is always available. After initial calibration at manu-
facturing, the manufacturer or end customer verifies the energ y
meter calibration. One convenient way to verify the meter
?
Select all the HCONFIG register bits.
calibration is to provide an output frequency proportional to the
Rev. A | Page 64 of 104
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